1. Field of the Invention
This invention relates to a method of manufacturing semiconductor devices and, more particularly, silicon gate MOS LSIs.
In the field of a silicon gate MOS LSI, there is a method which employs a diffused layer as a wiring layer.
2. Description of the Prior Art
In the formation of a diffused layer for a wiring layer, there has heretofore been put into practice a method in which, during the diffusion of an impurity for forming a source and a drain, the impurity is simultaneously diffused into a field portion. With reference to FIG. 2, after forming a wiring layer 11 of polysilicon on the field portion, an insulating film 15 is formed on a thermal oxidation film 2 on the surface of a substrate 1 by a CVD (chemical vapor deposition) process. Further, contact holes 15a are provided in the insulating film 15, and thus a connection between an aluminum wiring 16 and a diffused layer 3 for wiring within the substrate 1 is carried out.
With the above method, however, the perforation portion 2a of the thermal oxidation film 2 on the surface of the semiconductor substrate 1 is large, so that in forming the polysilicon wiring layer 11 on the thermal oxidation film 2, the area over which the polysilicon wiring layer 11 can be formed becomes small, it being difficult to enhance the degree of integration of the semiconductor device.
More specifically, the contact hole 15a requires a width or a diameter dimension of, for example, over 6.mu. . In order to prevent a short-circuit at the PN junction caused by the aluminum of the aluminum wiring 16 diffusing into the silicon substrate 1, a distance of. for example, over 4.mu. is needed between the peripheral edge of the contact hole 15a and the PN junction. For these reasons, the perforation portion 2a (the hole for diffusion for forming the diffused layer 3) in the thermal oxidation film 2 is inevitably so large that the width or the diameter dimension is, for example, over 14.mu. .